1. Field of the Invention
The present invention relates to a semiconductor device having an MIS type field effect transistor and a manufacturing method thereof.
2. Description of the Related Art
In recent years, as demands for a realization of a semiconductor integrated circuit with low power consumption and high operating speed or the like become rigid, a realization of a low power supply voltage and a fine element is desired. For this reason, in regard to a transistor element, attention is paid to a three-dimensional element in place of a conventional planar type element.
As the three-dimensional element, there has been known, e.g., an MOS transistor utilizing a fin-shaped semiconductor layer, i.e., a FinFET. The FinFET is superior in suppression of a short channel effect, a low subthreshold slope, high mobility and others as compared with other types of transistors.
FIGS. 1 and 2 show a structural example of the FinFET.
An insulating layer 2 is formed on a silicon substrate 1, and a fin-shaped silicon layer 3 is formed on the insulating layer 2. A so-called SOI substrate is constituted by the silicon substrate 1, the insulating layer 2 and the silicon layer 3.
A cap insulating layer 4 which is used as a mask when processing the silicon layer 3 is formed on the silicon layer 3. A gate electrode 6 is formed on each of two side surfaces of the silicon layer 3 in a direction y through a gate insulating layer 5. In this example, the gate electrode 6 on one side of the silicon layer 3 is separated from that on the other side of the same, but the both gate electrodes 6 may be electrically connected.
An area in the silicon layer 3 sandwiched by the gate electrodes 6 is a channel area 7. Further, in the silicon layer 3, source/drain areas 8 are formed on both sides of the channel area 7. A direction of a current flowing through the channel area 7 is a direction parallel to the surface of the silicon substrate 1, i.e., a direction x.
In case of operating such a FinFET as a fully depleted type element, in order to suppress a short channel effect, a fin in the channel area 7, i.e., a width Wch of the silicon layer 3 in the direction y (width of the channel area) must be set smaller than a gate length Lg. In each generation of LSI, however, since a dimension which can be processed into a minimum level by the lithography technology is usually coordinated with the gate length, it is very hard to form the channel area 7 having a width narrower than the gate length.
Furthermore, in the FinFET shown in FIGS. 1 and 2, the width Wch of the channel area 7 is equal to the width of the fin, i.e., the silicon layer 3 in the source/drain area 8 in the direction y. In this case, when the width Wch of the channel area 7 is reduced in order to suppress the short channel effect, the width of the fin in the source/drain area 8 in the direction y is also decreased. As a result, a parasitic resistance of the source/drain area 8 is increased, thereby lowering a drive current.
Moreover, an effective gate width (effective channel width) of the FinFET is twofold of a height h of the fin, i.e., the silicon layer 3. In order to increase the effective gate width, connecting a plurality of fins in parallel can suffice. On the other hand, in case of the FinFET, impurities must also be implanted into the side surfaces of the silicon layer 3 in order to form a source/drain area. Therefore, the source/drain area is usually formed by a tilted ion implantation method.
When a plurality of fins are connected to each other in parallel, however, a size of a part connecting a plurality of the fins is large. As a result, in the tilted ion implantation method, impurities based on the ion implantation do not spread in the entire source/drain formation planned area in each fin, and there is a problem that an area which is of an electroconductive type opposite to that of the source/drain area partially remains in the source/drain formation planned area.
In case of a planar (flat) transistor, as shown in FIG. 3, parasitic resistances consist of a silicide interface resistance Rc, a silicide sheet resistance Rs, a diffusion layer sheet resistance Rd immediately below the silicide and others, and these resistance components must be reduced in order to realize a high-speed operation.
As shown in FIG. 4, however, in an SOI structure, when a major part of the source/drain area is silicided, the diffusion layer sheet resistance Rd immediately below silicide is increased, and the parasitic resistance becomes large. Additionally, when all of the source/drain area is silicided, the parasitic resistance becomes extremely large. Thus, it is important to sufficiently assure a depth Xd of the diffusion layer immediately below silicide so as to prevent the diffusion layer sheet resistance Rd immediately below silicide from being increased.
In recent years, in order to realize high performances and high density of an element, fruition of fine transistors has been advanced, and a control over a current between the source and the drain by a gate electrode is becoming difficult (short channel effect).
Thus, nowadays, for example, an MOS transistor utilizing a fin-shaped semiconductor layer, i.e., a FinFET has been studied. The FinFET is superior in suppression of the short channel effect, a low subthreshold slope, high mobility and others as compared with other types of transistors.
FIG. 5 shows a structural example of the FinFET.
An insulating layer 2 is formed on a silicon substrate 1, and a fin-shaped silicon layer 3 is formed on the insulating layer 2. A so-called SOI substrate is constituted by the silicon substrate 1, the insulating layer 2 and the silicon layer 3.
A cap insulating layer 4 used as a mask when processing the silicon layer 3 is formed on the silicon layer 3. A gate electrode 6 is formed on two side surface of the silicon layer 3 in a direction y through gate insulating layers 5. In this example, the gate electrode on one side of the silicon layer 3 is electrically connected to the gate electrode 3 on the other side of the same so as to cut across the silicon layer 3, but the both gate electrodes 6 may be electrically separated from each other.
Sidewall insulating layers (sidewalls) 9 are formed on side surface of the gate electrode 6 in a direction x. A cap insulating layer 10 used as a mask when processing the gate electrode 6 is formed on the gate electrode 6.
Here, as shown in FIG. 6, an area in the silicon layer 3 sandwiched by the gate electrodes 6 is a channel area 7. Further, in the silicon layer 3, source/drain areas 8 and source/drain extension areas 8a are formed on both sides of the channel area 7. A direction of a current flowing through the channel area 7 is a direction parallel to a surface of the silicon substrate 1, i.e., the direction x.
Usually, in the FinFET shown in FIG. 5, there is adopted a silicide process which forms a silicide layer on the source/drain areas formed in the silicon layer 3. FIG. 6 shows the FinFET which has been subjected to the silicide process. Silicide layers 11 are formed in the silicon layer 3 (source/drain areas 8). In this example, there occur a problem that a major part of the source/drain areas 8 excluding areas immediately below the sidewall insulating layers 9 is silicided and a parasitic resistance is increased.
That is, the diffusion layer sheet resistance Rd immediately below silicide is increased, and the parasitic resistance becomes considerably high. Such a problem is also true in, e.g., transistors adopting an SOI structure and a double gate structure such as shown in FIG. 7.
Therefore, in the FinFET formed on the SOI substrate, it is necessary to propose a structure by which all of the channel portion is not silicided, reduce the diffusion layer sheet resistance Rd immediately below silicide and decrease the parasitic resistance.
As described above, in the prior art, it is hard to make a width of the fin (width of the channel area) in the channel area smaller than the gate length. Assuming the width of the channel area is smaller than the gate length, since this width is equal to the width of the fin in the source/drain area, there occur problems such as an increase in the parasitic resistance, a reduction in the drive current and others.
In order to control an effective channel width, when a structure that a plurality of fins are connected to each other in parallel is adopted, an area which is of an electroconductive type different from an electroconductive type of the source/drain area partially remains in the source/drain area.
Furthermore, when a silicide layer is provided on the source/drain area, a major part of the source/drain area is silicided since a width of the fin is small, and the diffusion layer sheet resistance immediately below silicide thereby becomes large.
Therefore, the following problems must be examined.
[1] Proposing a structure and a manufacturing method of a three-dimensional element such as a FinFET that {circle around (1)} a width of a channel area is smaller than a gate length, {circle around (2)} a width of a fin in a source/drain extension area is equal to or larger than the width of the channel area, and {circle around (3)} the width of the fin in the source/drain area is larger than the width of the channel area or the width of the fin in the source/drain extension area.
[2] Proposing a structure and a manufacturing method of a three-dimensional element such as a FinFET in which an effective channel width is controlled by the number of fins connected to each other in parallel rather than heights of the fins, and proposing a structure and a manufacturing method by which an area which is of an electroconductive type different from an electroconductive type of the source/drain area is prevented from partially remaining in the source/drain area.
[3] In regard to a silicide layer provided on the source/drain area in the fin, preventing a major part of the source/drain area from being silicided, reducing the diffusion layer sheet resistance immediately below silicide, thereby suppressing an increase in the parasitic resistance.